GO / RUST / CPP – Julia
If you have reached this post, perhaps you have been also wondering what are the benefits and drawbacks of the mentioned languages and which one to choose for your project or career. I have decided to create this post specifically to discuss some key differences between those languages. For that, I have decided to test them a little bit with one my favorite demos - computing Julia Fractals. The first thing about learning and testing something...
CUDA – MCC for Fingerprint Minutia Pairing
When I was literally thrown into biometrics, I had no idea how a fingerprint matching works. Unfortunately for me, the colleagues who were supposed to know that and even share that information with us didn’t know it either. No this is actually not a joke, its a kind of a very sad story, but I am not going to cry over my professional career here. Before we start, lets do a very quick introduction into fingerprint biometrics: A Minutia is a...
QSPI Flash Simulation
As the title of the post suggests, my intention was to originally write about QSPI (Quad SPI) only, but I would not have likely written about it when everything worked as intended, but as we already know, things are never that simple and the world is just cruel from the designer's perspective. It all started when I wanted to reuse a block of code at my project - Just a standard SPI communication interface to external Micron flash memory. Thing...
Understanding PCIe to AXI Bridge
The most basic setup of simulating/using PCIe on Xilinx FPGA / SoC devices is having a single endpoint (EP) and a single Root Complex (RC). One may accomplish this by instantiating only the base Hard IP Wrappers (Consisting of Physical Layer, Data Link Layer and Transaction Layer – Documented in PG213) in the TestBench and managing all the TLP packets and or messages in a custom user logic outside of the macro. This brings the greatest...
Simulating PCIe Hard IP for Ultrascale + Architecture
This time, I have decided to create a small and simple demo in order to show how to simulate PCIe interface (Without any DMA or PCIe bridge) for Xilinx devices as the PCIe is slowly becoming a standardized interface for FPGA in most applications from consumer electronics through Automotive up to Aerospace industry. As usual, I do target my favorite VCU118 platform this time with Vivado 2020.2. version. Unlike in my previous post with...
Aurora 8/10B Transceiver GTY Serdes
The times when designers used to calculate and adjust manually delays across PCBs to match a device’s requirements (Such as a memory or ADC/DAC interface) for a few megatransfers / second are definitely over nowadays. Even though they are still used on some prehistoric devices, they were replaced by advanced and more robust interfaces, which incorporated features like error correction, dynamic calibration and alignment. Not so long ago was...
Linux Kernel driver development for Zynq / ZynqMP
When I started to learn how to write linux kernel drivers, the very first suggestion was to avoid writing them. I dont have the same recommendation for anybody - writing linux kernel drivers requires some additional knowledge, precision and patience, but its not that difficult. After all, its only standard C languguage with some specific kernel functions. What actually makes writing kernel drivers more difficult is the reduced ability to debug...
Scrambling and Descrambling
I was recently asked for some support regarding the usage of Scramblers and Descramblers. So far to be honest, I didn’t had much time to dig-into the scramblers and descramblers problematic, but I do know, that there are interfaces such as the Xilinx’s Aurora 8/10 or Xilinx’s Aurora 64/66b, which uses these to enhance the protocol. Basically a scrambler/descrambler is a LSFR (Linear Shift Feedback Register) with a predefined length, custom...
FPGA LVDS Interfacing
Most of newer ADCs and DACs tend to use the JESD204b/c standards simply due to higher performance requirements – the ever growing need for more usable bandwidth, faster ADCs and DACs with increased resolution per sample and multi-channel implementations. The JESD internally uses Gigabit transceivers (Or MGTs – Multi Gigabit Transceivers ) with speeds of up to 32 Gbit/s per single lane (Xilinx Ultrascale + FPGA). This is indeed...
DSP IP Simulation
Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks, Filters, FFTs and other parts of some complex signal processing IPs. Checking whether they work as intended and that the DSP block doesn’t create any signal artifacts such as underflows or...
Hello and welcome to IrisCores! This will be “hopefully” mine personal technical blog for the upcomming decade(s). It took me a while to chose this domain name, but I have had several reasons to do that (Except for the fact that Iris is my favorite flower🌱) and even for choosing rather a subdomain for blogging – As the name suggest, it opens for more professional business usage, which is even why I have stayed away from DNS names, which would be more appropriate for my personality – rain, woods and cycling.
At the beginning of 2023, most of the posts from my previous domain ( https://www.beechwood.eu ) has been either revised and moved here or discarded in case the topic was outdated or a complete nonsense. Because beeing partially IT admin is sometimes fun, I have decided to keep maintaining the back-end, but to ease my pain a little bit and give me more freedom and less worries, the site is proudly powered by GCP ☁️
After graduating from Czech Technical University in Prague in 2016, I started working in GPGPU (General Purpose GPU ≈ CUDA ) for accelerating processing of large data sets and variety of computing intensive algorithms for signal and image processing. Soon after, I started my career as an FPGA designer and since then I have widely broadened my expertise among other related fields such as high speed data interfacing, communication on standartized interfaces such as AXI or PCIe and cooperation with software world and kernel drivers.
My dream is to live and work in peace in the coutryside, have a dog (or two 😇), a loving wife and a wonderfull family ☄️. I find joy in appreciations to my work, but I never expect to receive any. I learned the hard way that if you need something, you have to ask for it and go for it and that every small step you take brings you closer.
Love and kindness. Two words, that make life worth living