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QSPI Flash Simulation

QSPI Flash Simulation

As the title suggest, my intention was to originally write about QSPI only, but I would not have likely written about it when everything worked as intended, but as we already know, things are never that simple and the world is just cruel from the designer's...

Understanding PCIe to AXI Bridge

Understanding PCIe to AXI Bridge

The most basic setup of simulating/using PCIe on Xilinx FPGA / SoC devices is having a single endpoint (EP) and a single Root Complex (RC). One may accomplish this by instantiating only the base Hard IP Wrappers (Consisting of Physical Layer, Data Link Layer and...

Simulating PCIe Hard IP for Ultrascale + Architecture

Simulating PCIe Hard IP for Ultrascale + Architecture

This time, I have decided to create a small and simple demo in order to show how to simulate PCIe interface (Without any DMA or PCIe bridge) for Xilinx devices as the PCIe is slowly becoming a standardized interface for FPGA in most applications from...

Aurora 8/10B Transceiver GTY Serdes

Aurora 8/10B Transceiver GTY Serdes

The times when designers used to calculate and adjust manually delays across PCBs to match a device’s requirements (Such as a memory or ADC/DAC interface) for a few megatransfers / second are definitely over nowadays. Even though they are still used on some...

Linux Kernel driver development for Zynq / ZynqMP

Linux Kernel driver development for Zynq / ZynqMP

When I started to learn how to write linux kernel drivers, the very first suggestion was to avoid writing them. I dont have the same recommendation for anybody - writing linux kernel drivers requires some additional knowledge, precision and patience, but its not that...

FPGA LVDS Interfacing

FPGA LVDS Interfacing

  Most of newer ADCs and DACs tend to use the JESD204b/c standards simply due to higher performance requirements – the ever growing need for more usable bandwidth, faster ADCs and DACs with increased resolution per sample and multi-channel implementations....

DSP IP Simulation

DSP IP Simulation

  Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks,...

Petalinux

Petalinux

Petalinux is the Xilinx’s toolchain used for creating whole embedded Linux system for Xilinx devices. It is a convenient way of building all blocks necessary to create the bootable image for the targeted platform. But lets go to the very beginning. What you need for...

Fixed – Point

Fixed – Point

I have decided to create a small introduction to the concept of using fixed point representation in FPGA for DSP Operations. Because naturally in RTL design (VHDL, Verilog), there is no standard data format such as "integer or float", but only logic vector with bits...

Hello and welcome to IrisCores! This will be “hopefully” mine personal technical blog for the upcomming decade(s). It took me a while to chose this domain name, but I have had several reasons to do that (Except for the fact that Iris is my favorite flower 🌱) and even for choosing rather a subdomain for blogging – As the name suggest, it opens for more professional business usage, which is even why I have stayed away from DNS names, which would be more appropriate for my personality – rain, woods and cycling.

I will be slowly moving and revising posts from original domain https://www.beechwood.eu as the time goes.

After graduating from Czech Technical University in Prague in 2016, I started working in GPGPU (General Purpose GPU ) for accelerating processing of large data sets and variety of computing intensive algorithms for signal and image processing.  Soon after, I started my career as an FPGA designer and since then I have widely broadened my expertise among other related fields such as high speed data interfacing, communication on standartized interfaces such as AXI or PCIe and cooperation with software world and kernel drivers.

My dream is to live and work in peace in the coutryside, have a dog (or two 🐾🐾), a loving wife and a wonderfull family ☄️. I find joy in appreciations to my work, but I never expect to receive any. I learned the hard way that if you need something, you have to ask for it and go for it and that every small step you take brings you closer.

Love and kindness. Two words, that make life worth living

Vojtech

FPGA Designer