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GO / RUST / CPP – Julia

GO / RUST / CPP – Julia

GO / RUST / CPP – Julia If you have reached this post, perhaps you have been also wondering  what are the benefits and drawbacks of the mentioned languages and which one to choose for your project or career. I have decided to create this post specifically to...
CUDA – MCC for Fingerprint Minutia Pairing

CUDA – MCC for Fingerprint Minutia Pairing

CUDA – MCC for Fingerprint Minutia Pairing When I was literally thrown into biometrics, I had no idea how a fingerprint matching works.  Unfortunately for me, the colleagues who were supposed to know that and even share that information with us didn’t know it...
QSPI Flash Simulation

QSPI Flash Simulation

QSPI Flash Simulation As the title of the post suggests, my intention was to originally write about QSPI (Quad SPI) only, but I would not have likely written about it when everything worked as intended, but as we already know, things are never that simple and the...
Understanding PCIe to AXI Bridge

Understanding PCIe to AXI Bridge

The most basic setup of simulating/using PCIe on Xilinx FPGA / SoC devices is having a single endpoint (EP) and a single Root Complex (RC). One may accomplish this by instantiating only the base Hard IP Wrappers (Consisting of Physical Layer, Data Link Layer and...
Simulating PCIe Hard IP for Ultrascale + Architecture

Simulating PCIe Hard IP for Ultrascale + Architecture

This time, I have decided to create a small and simple demo in order to show how to simulate PCIe interface (Without any DMA or PCIe bridge) for Xilinx devices as the PCIe is slowly becoming a standardized interface for FPGA in most applications from consumer...