Select Page
Aurora 8/10B Transceiver GTY Serdes

Aurora 8/10B Transceiver GTY Serdes

The times when designers used to calculate and adjust manually delays across PCBs to match a device’s requirements (Such as a memory or ADC/DAC interface) for a few megatransfers / second are definitely over nowadays. Even though they are still used on some...
Linux Kernel driver development for Zynq / ZynqMP

Linux Kernel driver development for Zynq / ZynqMP

When I started to learn how to write linux kernel drivers, the very first suggestion was to avoid writing them. I dont have the same recommendation for anybody – writing linux kernel drivers requires some additional knowledge, precision and patience, but its not...
Scrambling and Descrambling

Scrambling and Descrambling

Scrambling and Descrambling I was recently asked for some support regarding the usage of Scramblers and Descramblers. So far to be honest, I didn’t had much time to dig-into the scramblers and descramblers problematic, but I do know, that there are interfaces such as...
FPGA LVDS Interfacing

FPGA LVDS Interfacing

  Most of newer ADCs and DACs tend to use the JESD204b/c standards simply due to higher performance requirements – the ever growing need for more usable bandwidth, faster ADCs and DACs with increased resolution per sample and multi-channel implementations....
DSP IP Simulation

DSP IP Simulation

  Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks, Filters,...