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QSPI Flash Simulation

QSPI Flash Simulation

QSPI Flash Simulation As the title of the post suggests, my intention was to originally write about QSPI (Quad SPI) only, but I would not have likely written about it when everything worked as intended, but as we already know, things are never that simple and the...
Understanding PCIe to AXI Bridge

Understanding PCIe to AXI Bridge

The most basic setup of simulating/using PCIe on Xilinx FPGA / SoC devices is having a single endpoint (EP) and a single Root Complex (RC). One may accomplish this by instantiating only the base Hard IP Wrappers (Consisting of Physical Layer, Data Link Layer and...
Simulating PCIe Hard IP for Ultrascale + Architecture

Simulating PCIe Hard IP for Ultrascale + Architecture

This time, I have decided to create a small and simple demo in order to show how to simulate PCIe interface (Without any DMA or PCIe bridge) for Xilinx devices as the PCIe is slowly becoming a standardized interface for FPGA in most applications from...
Aurora 8/10B Transceiver GTY Serdes

Aurora 8/10B Transceiver GTY Serdes

The times when designers used to calculate and adjust manually delays across PCBs to match a device’s requirements (Such as a memory or ADC/DAC interface) for a few megatransfers / second are definitely over nowadays. Even though they are still used on some...
Linux Kernel driver development for Zynq / ZynqMP

Linux Kernel driver development for Zynq / ZynqMP

When I started to learn how to write linux kernel drivers, the very first suggestion was to avoid writing them. I dont have the same recommendation for anybody – writing linux kernel drivers requires some additional knowledge, precision and patience, but its not...
FPGA LVDS Interfacing

FPGA LVDS Interfacing

  Most of newer ADCs and DACs tend to use the JESD204b/c standards simply due to higher performance requirements – the ever growing need for more usable bandwidth, faster ADCs and DACs with increased resolution per sample and multi-channel implementations....